Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.2 9/5/84; site ism780c.UUCP
Path: utzoo!watmath!clyde!burl!ulysses!gamma!epsilon!zeta!sabre!petrus!bellcore!decvax!ittatc!dcdwest!sdcsvax!sdcrdcf!ism780c!tim
From: tim@ism780c.UUCP (Tim Smith)
Newsgroups: net.micro
Subject: Re: MC68008
Message-ID: <173@ism780c.UUCP>
Date: Wed, 18-Dec-85 15:54:50 EST
Article-I.D.: ism780c.173
Posted: Wed Dec 18 15:54:50 1985
Date-Received: Fri, 20-Dec-85 05:28:26 EST
References: <35@gumby.UUCP> <88800001@haddock.UUCP>
Reply-To: tim@ism780c.UUCP (Tim Smith)
Organization: Interactive Systems Corp., Santa Monica, CA
Lines: 32

>	68008	8-bit external
>	68000	16-bit external
>	68010	32-bit external
>	68020	32-bit external w/VMM

Actually:

	68008   8-bit data bus, ?? bit address bus

	68000   16-bit data bus, 24 bit address bus

	68010   same as 68000 except bus error saves enough information
		to restart, vectors can be relocated, and more efficient
		microcode for some instructions

	68012   same as 68010 except that address bus is 31 bits (
		  *             **
		a0 - a29 and a31   ).

	68020   32 bit data and address buses, on-chip cache, new
		instructions, pipelined, more addressing modes,
		coprocessor interface.

*
 Actually, there isn't an a0: the chip gives a word address, and there are
 two signals that tell if it is the upper byte, lower byte, or both, that
 is desired, but it is simpler to just pretend that there is an a0.

**
  No, I have no idea why they did it this way!
-- 
Tim Smith       sdcrdcf!ism780c!tim || ima!ism780!tim || ihnp4!cithep!tim