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From: Andreas.Nowatzyk@UNH.CS.CMU.EDU
Newsgroups: mod.computers.workstations
Subject: Re: Need help in evaluating H/W and S/W
Message-ID: <1986.2.12.2.12.50.Andreas.Nowatzyk@unh.cs.cmu.edu>
Date: Tue, 11-Feb-86 21:21:29 EST
Article-I.D.: unh.1986.2.12.2.12.50.Andreas.Nowatzyk
Posted: Tue Feb 11 21:21:29 1986
Date-Received: Wed, 12-Feb-86 21:49:46 EST
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Approved: works@red.rutgers.edu

There are not just disgruntled ex-employees that have low opinions on
Daisy products. You can add scores of frustrated user and system-
maintainer. Based on 2.5 years experience with the Daisy-workstations
(both the low-end PC/AT version and the high-end Mega-Logician with
PMX) as both user and system maintainer, I would strongly recommened
to take a very carefull look at this brand of machines before buying
one.

The workstation was originally based on an Intel 8086/87 processor.
It was later 'upgraded' to the 80286/287 processor. This helps to
understand several problems. The worst of which can be contributed to
the dreadfull 64K byte segments, which caused tons of rather
arbitrary limitations (say a limit of the number of symbol names for
components on a drawing page). This caused a lot of frustration.
These limitations slowly vanished over time, but quite a few are
still around. The cost of switching to a larger address mode was a
substantial loss in performance. The machines are sssslllooowww!
(notable execption: the hardware accellerators are reasonably fast).
The interactive programs (various editors, utilities and some
compilers) are very slow compared to similar programs on SUN's. Part
of this is due to the use of a large number of intermediate files
(again a consequence of the memory addressing problems). Practically
all mainstream design applications take at least 30 sec. to load
(that is with a fast Eagle Disk upgrade).

As mentioned before, the UNIX-like windowing system has finally
arrived (in December '85), but it is quite buggy. Actually it would
be quite nice if it were about 3times faster and had 3times fewer
bugs. The later will probably happen, but it is extremly rare that
anything became faster with a new release. Also, experience has it
that all new releases introduce a decent number of new, subtle bugs
along with with great improvement like " '=' have to be replaced with
':=' except if .... - please update your files". The current software
evolved by adding features to a basic design that did not anticipate
this growth. As a result, it is in need of a fundamental rewrite from
scratch, but that will not happen because of the existing customer
base.

An other major problem is that the system is hard to learn. This is
mainly due to:
 - A voluminous, but incomplete and poorly organized documentation.
 - Inconsistent command interfaces (you can tell the different
   authors apart by their creativity of using different syntax for
   similar functions: there are lisp types, pascal freaks, unix
   wizzards...)  Much fun, but can be confusing.
 - IBM style Hex-listings please real programmers, but not
   necessarily new user
 - Most intermediate file uses undocumented binary files to ensure
   that that user can't figure out what is going on (for example:
   some bugs in the Drawing EDitor can insert invisibale information
   in a file that either crashes the editor whenever that page is
   touched or (even better) an application 2 processing steps later).
   Experience with ASCII based CAD systems on VAXen or SUN's show
   that superior performance is possible with readable files.
 - Several special purpose languages needs to be learned. Lacking the 
   power of a real programming language, a large number of special
   function calls are added to bridge the gaps.
 - JCL fans will love the various control files, parameter files,
   configuration files, format files. It helps if you remember the
   Fortran Format edit commands...

I don't think that anyone would consider using these systems for
anything else but CAD work unless he has no other options. As
mentioned before: the accelerators are fast (say 30 min to simulate a
40K gate chip, but it takes about 24h to compile such a design).

Many opinion expressed in this post are shared by other Daisy user at
different sites. If you want more information/horror stories feel
free to contact me directly (this is not too interesting to the
entire net).

  Cheers  --  Andreas           Arpa: agn@vlsi.cs.cmu.edu
                                uucp:  ...!seismo!vlsi.cs.cmu.edu!agn