Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84; site mips.UUCP Path: utzoo!watmath!clyde!burl!ulysses!bellcore!decvax!decwrl!glacier!mips!mash From: mash@mips.UUCP (John Mashey) Newsgroups: net.arch Subject: Re: IBM RT PC, 801, RISC horserace, etc. Message-ID: <298@mips.UUCP> Date: Fri, 31-Jan-86 11:11:25 EST Article-I.D.: mips.298 Posted: Fri Jan 31 11:11:25 1986 Date-Received: Sat, 1-Feb-86 21:26:15 EST References: <1328@sdcsvax.UUCP> <5100001@ccvaxa> <449@hoptoad.uucp> <1220@lll-crg.ARpA> Organization: MIPS Computer Systems, Mountain View, CA Lines: 66 Eugene D. Brooks III (lll-crg!brooks) writes: > > The RISC development to watch is the Clipper chip set from Fairchild. > It is more up to date technology, has on chip floating point and seperate > single chip cache and memory management support. 1) One can argue the merits of one chip (set) over another, using many different criteria. Whether something is or isn't a RISC, or better, how RISCy it is, is only one attribute, and I wouldn't suggest that it is the primary one. 2) Nevertheless, this kind of discussion may confuse the issue, i.e., exactly what a RISC is and why gets terribly confused when people apply the term to radically different architectures. Fairchild's own literature [I have a lot of it] claims correctly that it applies some RISC ideas, not that it is a RISC. 3) A fundamental idea of RISC is to reduce the number of machine cycles per instruction (or better, per Mips-equivalent). Here are some numbers, (please don't niggle over fractions, this is all approximate): CHIP CLOCK Mips CLOCKS/Mips 68020 16Mhz 2 8 Clipper 33 5 6 ROMP 6 2 3 4) No one believes the 68020 is a RISC. Most people believe ROMP is a RISC [although be careful, it is of the "low-cost RISC" style, i.e., designed for efficient cacheless operation, rather than all-out performance.]. If you use the metric of clocks/mips, you can judge for yourself whether the Clipper is more like a ROMP or more like a 68020. 5) Why do people care about clocks/Mips? ANS: because the clock speed ends up being a fundamental limiting factor, especially as you cram more and more on a few chips. Be very careful to separate the effects of circuit technology from architecture: from the circuit side, faster clock = more impressive. From the architecture side, faster clock (for the same delivered performance) = LESS impressive. 6) Growth paths. I have no idea what IBM is up to. Nevertheless, one has to believe that a ROMP-style design has a lot more headroom for clock rate improvements than do the others listed. Here is a hypothetical question: if you can have a 5Mips Clipper at 33Mhz in 1986, when can you get one that might at go at, say, 10Mips, i.e., around 66Mhz? 7) The next month or so should be interesting. UNIFORUM has one RISC vs CISC debate. IEEE COMPCON (San Francisco, March 4-6) has the following free-for-all: a) a RISC vs CISC debate b) a full session (I think) on HP Spectrum, or whatever it will be called by then. c) a full session by Fairchild on Clipper and d) a full session by MIPS Computer Systems on our stuff [finally, out of the closet!] 8) Again, I emphasize again that I'm not proposing that RISC = GOOD, CISC = bad, but that one must look at every architecture on its own merits, rather than lumping a raft of rather different architectures under the same label. -- -john mashey UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mash DDD: 415-960-1200 USPS: MIPS Computer Systems, 1330 Charleston Rd, Mtn View, CA 94043