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From: stubbs@ncr-sd.UUCP (Jan Stubbs)
Newsgroups: net.arch
Subject: Re: dhrystones on the IBM RT PC
Message-ID: <402@ncr-sd.UUCP>
Date: Fri, 7-Feb-86 18:55:53 EST
Article-I.D.: ncr-sd.402
Posted: Fri Feb  7 18:55:53 1986
Date-Received: Sun, 9-Feb-86 06:41:17 EST
References: <316@yetti.UUCP> <1000008@uicsrd>
Reply-To: stubbs@ncr-sd.UUCP (0000-Jan Stubbs)
Distribution: net
Organization: NCR Corporation, San Diego
Lines: 31

In article <1000008@uicsrd> mcgrath@uicsrd.CSRD.UIUC.EDU writes:
>
>We also saw a demo.  The IBM rep "didn't want to talk about floating point"
>with the implication that it didn't really exist yet.  Who knows?
>
I saw the IBM/RT at uniforum. A friendly person who claimed to head up
the chip development team at Austin, Texas said the following:

The floating point chip is a National Semiconductor NS32????. The ROMP is 
not an 801 (which was a discrete system) but used some similar concepts.
It has a 23Mhz clock but uses four clocks per cycle which gives it a
170NS cycle time. 80 out of 120 instructions execute in 1 cycle, but the
average cycles per instruction was >3. Load and store take 5 cycles each.
There is no cache. There is a 16 word instruction buffer. The MMU was
added late in the design (presumably to run UNIX??). There are 16 General
purpose registers.

The operating system emulates DOS commands, so I believe that copy a b
does the same as cp a b if you are in DOS mode. Only one person
can use the 80286 at a time. The 80286 is an option. Xenix was also
shown in the booth along with some applications such as accounting
and engineering stuff.

I also saw a 12 cpu Encore Multimax running a similated load with 128
processes. While this was running I logged on and ran a 'C' compile, which
completed in a very reasonable time considering the load.


Jan Stubbs    ....sdcsvax!ncr-sd!stubbs
NCR Corp.
San Diego