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From: freak@nsc.UUCP (Curt Mayer)
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <3421@nsc.UUCP>
Date: Thu, 13-Feb-86 04:19:59 EST
Article-I.D.: nsc.3421
Posted: Thu Feb 13 04:19:59 1986
Date-Received: Fri, 14-Feb-86 07:05:48 EST
References: <946@garfield.UUCP>
Reply-To: freak@nsc.UUCP (Curt Mayer)
Organization: The Zen Room
Lines: 24
Keywords: RISC, Belly laughs, CDC 6600

In article <946@garfield.UUCP> jeff1@garfield.UUCP (Jeff Sparkes) writes:
>
>	We are currently designing a RISC chip and are wondering how
>few addressing modes we can get away with.  Right now we have register
>direct and register indirect.  The question is, is this enough?  What do
>people as programmers and/or designers think is a minimum set of addressing
>modes?  We can get away with just these two (I hope!), but doing some things
>requires a lot of convoluted code.
>	I guess followups should go to net.arch, just to keep them all in the
>same place.

:-)
i had quite a bit of fun looking at bizarre ways to simulate the immediate
addressing mode. maybe you could play with XORs and SHIFTs to get numbers
into registers in the first place.

Take a look at the CDC Cybers designed by Seymour Cray and friends in the
early 60's.  Heap Big Nasty Machines.  I watch with amusement whenever some
university comes up with a new, novel thingy that Cray came up with 20
years ago. 

the more that things change, the more they stay the same

	curt