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Posting-Version: version B 2.10.2 GARFIELD 20/11/84; site garfield.UUCP
Path: utzoo!utcsri!ubc-vision!garfield!jeff1
From: jeff1@garfield.UUCP
Newsgroups: net.arch,net.lang
Subject: Addressing modes
Message-ID: <946@garfield.UUCP>
Date: Tue, 11-Feb-86 15:30:33 EST
Article-I.D.: garfield.946
Posted: Tue Feb 11 15:30:33 1986
Date-Received: Tue, 11-Feb-86 21:45:52 EST
Sender: news@garfield.UUCP
Reply-To: jeff1@garfield.UUCP (Jeff Sparkes)
Followup-To: net.arch
Organization: Memorial U. of Nfld. C.S. Dept., St. John's
Lines: 13


	We are currently designing a RISC chip and are wondering how
few addressing modes we can get away with.  Right now we have register
direct and register indirect.  The question is, is this enough?  What do
people as programmers and/or designers think is a minimum set of addressing
modes?  We can get away with just these two (I hope!), but doing some things
requires a lot of convoluted code.
	I guess followups should go to net.arch, just to keep them all in the
same place.

Jeff Sparkes
jeff1%garfield.mun.cdn@ubc.csnet  <- preferred route
{allegra,seismo,psuvax1,utcsri}!garfield!jeff1  (I don't trust ihnp4 any more)