Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/5/84; site gondor.UUCP Path: utzoo!watmath!clyde!cbosgd!ukma!psuvm.bitnet!psuvax1!gondor!polo From: polo@gondor.UUCP (Michael S. Polo) Newsgroups: net.arch,net.micro Subject: Memory (also RT address space) Message-ID: <1994@gondor.UUCP> Date: Sat, 8-Feb-86 19:06:36 EST Article-I.D.: gondor.1994 Posted: Sat Feb 8 19:06:36 1986 Date-Received: Tue, 11-Feb-86 06:31:58 EST Reply-To: polo@gondor.UUCP (Mikeael S. Polo) Organization: Pennsylvania State Univ. Lines: 13 Xref: watmath net.arch:2493 net.micro:13752 I heard that Intel is working on 64M and 128M-bit memory chips. I talked to a representative from TI a while ago, and they remarked that they were working on 32M chips. Does anyone know what kind of time frame this will fit into? Is this the near future? This could also be the reasoning behind the 40 bit virtual address space of the RT, though I don't have any idea of what the physical address space is. With large scale memory chips like these, the thought is a little mind boggling. Mike Polo ...allegra!psuvax!gondor!polo