Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.2 9/5/84; site mnetor.UUCP
Path: utzoo!utcs!mnetor!michael
From: michael@mnetor.UUCP (Michael Barnea)
Newsgroups: net.micro.68k
Subject: Re: Re: VMEbus problems
Message-ID: <3000@mnetor.UUCP>
Date: Tue, 28-Jan-86 14:40:47 EST
Article-I.D.: mnetor.3000
Posted: Tue Jan 28 14:40:47 1986
Date-Received: Tue, 28-Jan-86 16:23:49 EST
References: <1201@gitpyr.UUCP> <1038@ecsvax.UUCP>
Organization: Computer X (CANADA) Ltd., Toronto, Ontario, Canada
Lines: 27

> 
> 
> This info comes from Howard Crawford at Telex Terminals in Raleigh NC.
> They have been having similar problems using the 8530 with a 64180.
> The problem apparently is in the interrupt ack versus vector read
> timing. The setup time required by the 8530 between int ack and read
> must be met. Otherwise the vector may come out meaningless. There must
> also be the right setup time between rec clock and chip clock. The
> exact values are in the databooks.
> It is also interesting to note that Apple says not to access the 8530
> in the Mac more often than once every 2.2 usec. (from Inside Macintosh)
> so there must be a fair amount of settling inside the chip.
> Wayne Sung
> N C State University

An article in EDN of April 4 1985 brings an example
of interfaces to overcome the inherent 8530 limitations.
Although the circuits deal with Intel processor, they
are easily adaptable to 68k. The delay in an example
circuit can be of course implemented digitally.


Michael Barnea, Motorola New Enterprises, Toronto, Canada
-- 
Michael Barnea,
UUCP: {allegra, linus, ihnp4, decvax}!utzoo!mnetor!michael
BELL: (416)-475-8980 ext. 308