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Posting-Version: version B 2.10.2 9/18/84; site looking.UUCP
Path: utzoo!watmath!looking!jan
From: jan@looking.UUCP (Jan Gray)
Newsgroups: net.micro.atari
Subject: Re: Bus contention
Message-ID: <489@looking.UUCP>
Date: Tue, 28-Jan-86 10:13:00 EST
Article-I.D.: looking.489
Posted: Tue Jan 28 10:13:00 1986
Date-Received: Wed, 29-Jan-86 04:27:32 EST
References: <2048@watdcsu.UUCP>
Reply-To: @looking.UUCP (Jan Gray)
Organization: Looking Glass Software Ltd. Waterloo, Ontario
Lines: 46
Summary: 

In article <2048@watdcsu.UUCP> dmcanzi@watdcsu.UUCP (David Canzi) writes:
>To refresh a 640 by 400 bit screen 70 times per second from memory 16
>bits wide requires reading memory 1.12 million times per second.  It
>takes 4 clock cycles (minimum) for the processor to read a word from
>memory.  I would assume the same applies to the screen logic, *plus*
>the time it takes to get control of the bus before reading, and
>relinquish it after reading.  With an 8 megahertz clock, the screen
>must be slowing down the processor by at least a factor of 2.
>
>Or have I made a mistaken assumption somewhere?
>
>David Canzi

Yes.  Although it takes 4 clocks for the processor to read a word from
memory, that doesn't mean it takes 4+4=8 clocks for both the processor
and the video display circuitry to get a word from memory.  If memory
is fast enough, it is possible to run the processor at ALMOST full
speed and insert video display cycles in between processor cycles.

A rough (from memory) diagram of a 68000 memory access:

(ns)	0	       125	       250	       375	       500
(clock)	|	1	|	2	|	3	|	4	|
	|		|		|		|		|
	| setup address	| start memory	| wait for mem	| deassert address
	| and control	| cycle		| acknowledge	| and control	|
	| signals	|		|		| signals	|

The 68000 only needs access to the RAMS during clocks 2 and 3 (as I have
indicated them above).  If hardware was clever enough, and memory
fast enough, you could sneak in a video fetch during cycles 4 and 1.

This is exactly what the ST, Macintosh and Amiga do.  They all have fast
memory (250 ns -- ST, 280ns Amiga, ?? Mac) and stick a video (or whatever)
cycle in there with the processor access.

Why did I say "ALMOST full speed"?  The 68000 is an asynchronous part
(that is to say, its not synchronized with the bus), but the scheme
I presented above IS synchronous!  The arbitration circuitry inserts
wait states until the processor gets synchronized to the bus.  So long as
the 68000 executes instructions which take a multiple of 4 clocks, it will
stay synchronized.  Unfortunately there are a few instructions which
take 2 (mod 4) clocks, and which cause the hardware to insert wait states
(effectively throwing away 2 clocks).

Jan Gray		Looking Glass Software		(519) 884-7473