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Path: utzoo!watmath!clyde!cbosgd!gatech!gt-stratus!gitpyr!kludge
From: kludge@gitpyr.UUCP (Scott Dorsey)
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <1404@gitpyr.UUCP>
Date: Thu, 13-Feb-86 23:13:58 EST
Article-I.D.: gitpyr.1404
Posted: Thu Feb 13 23:13:58 1986
Date-Received: Sat, 15-Feb-86 02:21:53 EST
References: <946@garfield.UUCP> <3421@nsc.UUCP>
Reply-To: kludge@gitpyr.UUCP (Scott Dorsey)
Organization: Georgia College Of Universal Knowledge
Lines: 26
Keywords: RISC, Belly laughs, CDC 6600

In article <946@garfield.UUCP> jeff1@garfield.UUCP (Jeff Sparkes) writes:
>
>	We are currently designing a RISC chip and are wondering how
>few addressing modes we can get away with.  Right now we have register
>direct and register indirect.  The question is, is this enough?  What do
>people as programmers and/or designers think is a minimum set of addressing
>modes?  We can get away with just these two (I hope!), but doing some things
>requires a lot of convoluted code.
>	I guess followups should go to net.arch, just to keep them all in the
>same place.
 
   Well, I am a big fan of MOVQ type instructions, which move a 4-bit
literal field within the instruction into a register or address.  If you
have 32-bit instructions, there is plenty of room, and even on a 16-bit
machine, if the instruction set is small then there should be no problem.
For a good example, see the 32000 series.  It's not a RISC machine, but
its code density is admirable.  I don't know just how bad the difficulty
of handling such an instruction is, but with a barrel shifter hanging off
the side, it shouldn't be bad.
  I like double and triple indirection.  They probably don't justify
themselves in terms of speed, though.  But I still like them.
  I like indexed addressing (INDEX+constant)...and an instruction that
sums two values and gets the address pointed to by the sum would be cute
for array manipulation.  But then, I'm just an assembly hacker.