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From: hansen@mips.UUCP (Craig Hansen)
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <340@mips.UUCP>
Date: Thu, 13-Feb-86 22:51:16 EST
Article-I.D.: mips.340
Posted: Thu Feb 13 22:51:16 1986
Date-Received: Sat, 15-Feb-86 04:38:55 EST
References: <946@garfield.UUCP>
Organization: MIPS Computer Systems, Mountain View, CA
Lines: 46

> 	We are currently designing a RISC chip and are wondering how
> few addressing modes we can get away with.  Right now we have register
> direct and register indirect.  The question is, is this enough?  What do
> people as programmers and/or designers think is a minimum set of addressing
> modes?  We can get away with just these two (I hope!), but doing some things
> requires a lot of convoluted code.
> 
> Jeff Sparkes
> jeff1%garfield.mun.cdn@ubc.csnet  <- preferred route
> {allegra,seismo,psuvax1,utcsri}!garfield!jeff1  (I don't trust ihnp4 any more)

Did you forget to mention an immediate operand addressing mode?

I fear you are asking the wrong question.  Are you trying to minimize the
number of addressing modes, or maximize performance?  The RISC design
approach involves selecting a small set of operations that minimize the
product of (the dynamic number of instructions executed) * (average
instruction execution time).  By minimizing only the first of these
parameters, you get the classic overwrought CISC design, and by minimizing
only the second, you may drastically increase the number of instructions
executed, and get a less than optimum design.

The number of addressing modes alone isn't enough to make the decision; what
you provide in the way of the remaining operations is important too.
For example, with a suitable add register instruction, you can synthesize
indexed addressing, an add immediate instruction can synthesize
base-displacement addressing, and a shift instruction can be used to
synthesize index-shifted addressing.

As you say, keeping a small set of addressing modes will make the path
length (instruction count) of some operations rather high, but I would
expect that you would find relatively little usage of very complicated
addressing modes, and further, that these complicated modes can be
synthesized from a smaller set of operations.

Further, if you are trying to design a really practical RISC machine, you
must examine how machine code is generated and linked, as these operations
are just as critical to the selection of appropriate addressing structures
as the hardware trade-offs are.


Evurthin' tastes better when it sits on a RISC.

Craig Hansen
MIPS Computer Systems
...!decvax!decwrl!glacier!mips!hansen