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From: gnu@hoptoad.uucp (John Gilmore)
Newsgroups: net.arch,net.micro.mac,net.micro.68k
Subject: Re: timing loops
Message-ID: <530@hoptoad.uucp>
Date: Sat, 15-Feb-86 23:58:24 EST
Article-I.D.: hoptoad.530
Posted: Sat Feb 15 23:58:24 1986
Date-Received: Mon, 17-Feb-86 05:24:56 EST
References: <156@motatl.UUCP>
Organization: Nebula Consultants in San Francisco
Lines: 19
Xref: watmath net.arch:2531 net.micro.mac:4684 net.micro.68k:1486

In article <156@motatl.UUCP>, wayne@motatl.UUCP (R.W.McGee) writes:
> The use of software timing loops on an asyncronous
> microprocessor should be discouraged...Public floggings would provide
> a cure, but would be hard to implement.

People who design microprocessors, who don't want software to depend
on the timings of individual instructions in particular systems,
should provide a system-independent way to delay for a specified
amount of time.  We use whatever you give us, guys!

E.g. in meeting the recovery time of a particularly good USART chip
with a horrible bus interface, the Z8530, you need to wait 2.2us
between writes to it.  Give me a good way to wait 2.2us *without*
depending on instruction timing, and I'll consider your request.

PS:  if your answer is "add more chips", a lot of people will cheap
out and use "free" software timing loops.
-- 
John Gilmore  {sun,ptsfa,lll-crg,ihnp4}!hoptoad!gnu   jgilmore@lll-crg.arpa