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From: mat@amdahl.UUCP (Mike Taylor)
Newsgroups: net.arch,net.micro.mac,net.micro.68k
Subject: Re: timing loops
Message-ID: <2795@amdahl.UUCP>
Date: Sun, 16-Feb-86 20:50:04 EST
Article-I.D.: amdahl.2795
Posted: Sun Feb 16 20:50:04 1986
Date-Received: Tue, 18-Feb-86 03:30:39 EST
References: <156@motatl.UUCP> <530@hoptoad.uucp>
Organization: Amdahl Corp, Sunnyvale CA
Lines: 14
Xref: watmath net.arch:2538 net.micro.mac:4701 net.micro.68k:1488

In article <530@hoptoad.uucp>, gnu@hoptoad.uucp (John Gilmore) writes:
> E.g. in meeting the recovery time of a particularly good USART chip
> with a horrible bus interface, the Z8530, you need to wait 2.2us
> between writes to it.  Give me a good way to wait 2.2us *without*
> depending on instruction timing, and I'll consider your request.

Well, on a *real* computer, you just set the TOD clock comparator for
now+2.2 us. and go do something useful while you wait.  Sorry, couldn't
resist.

-- 
Mike Taylor                        ...!{ihnp4,hplabs,amd,sun}!amdahl!mat

[ This may not reflect my opinion, let alone anyone else's.  ]