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From: jack@boring.uucp (Jack Jansen)
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <6777@boring.UUCP>
Date: Sun, 16-Feb-86 19:27:52 EST
Article-I.D.: boring.6777
Posted: Sun Feb 16 19:27:52 1986
Date-Received: Tue, 18-Feb-86 03:36:14 EST
References: <946@garfield.UUCP> <1417@sdcsvax.UUCP>
Reply-To: jack@mcvax.UUCP (Jack Jansen)
Organization: AMOEBA project, CWI, Amsterdam
Lines: 37
Apparently-To: rnews@mcvax

In article <1417@sdcsvax.UUCP> darrell@sdcsvax.UUCP (Darrell Long) writes:
>You should include an indexed addressing mode.  Array manipulation
>is a very common thing, and indexed mode helps the code generation
>alot!
No, please..... The idea of a RISC architecture is to *eliminate*
all fancies like indexed addressing. The point is, a compiler will
have a terrible time generating code for it. As an example, the line

	a = arr[b];	/* a=r0, b=r1 */
could be translated into
	mov	arr(r1),r0	If 'arr' is static/external, and
				sizeof(arr[0]) = 1, or
	mov	arr(lb,r1.b),r0
	mov	arr(lb,r1.w),r0
	mov	arr(lb,r1.d),r0	If the machine knows double indexing
				with operand width specification
				and the array sits on the stack
				*and* sizeof(arr[0]) is 1,2 or 4; or
	mov	r1,r2
	mul	#sizeof(arr[0]), r2
	add	#arr,r2
	add	lb,r2
	mov	*r2, r0		If all else fails.

(And a lot of intermediate forms, depending on the machine).
Now, the point is that most compiler-writers don't have the time
to let their compiler look for all those fancy addressing modes
it might be able to use. And even if they do incorporate these
features, they'll make the compiler much bigger and hairier (and
buggier).

The idea behind a RISC machine is to have instructions with only
limited capabilities (when compared to a CISC machine, like a
VAX or a 32032), but to make them *fast*.
-- 
	Jack Jansen, jack@mcvax.UUCP
	The shell is my oyster.