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From: kludge@gitpyr.UUCP (Scott Dorsey)
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <1433@gitpyr.UUCP>
Date: Mon, 17-Feb-86 14:24:33 EST
Article-I.D.: gitpyr.1433
Posted: Mon Feb 17 14:24:33 1986
Date-Received: Tue, 18-Feb-86 04:06:59 EST
References: <946@garfield.UUCP> <1417@sdcsvax.UUCP> <6777@boring.UUCP>
Reply-To: kludge@gitpyr.UUCP (Scott Dorsey)
Organization: Georgia College Of Universal Knowledge
Lines: 23

In article <6777@boring.UUCP> jack@mcvax.UUCP (Jack Jansen) writes:
>No, please..... The idea of a RISC architecture is to *eliminate*
>all fancies like indexed addressing. The point is, a compiler will
>have a terrible time generating code for it. As an example, the line

   That is absolutely true, but who is to say just WHAT instructions
and adressing modes are really needed... That is to say which instructions
are worth the amount of time to decode them vs. the amount of time 
required to use equivalent low-level instructions?  Depending on the
architecture of the machine, this varies a lot.  Who is to say what
the optimum architectural complexity vs. instruction set complexity
is?  Without fancy register stacks, RISC machines DO tend to execute
faster than their CISC contemporaries doing most problems.  Maybe this
is due to the increase in compiler simplicity, in which case the idea
would seem to me to build a compiler which can better use the CISC.

-------
 Disclaimer:  I wouldn't like to code assembly on a RISC machine, but
             this message is being sent from one, and WOW!  Is it fast!

Scott Dorsey
ICS Programming Lab, Georgia Insitute of Technology, Atlanta Georgia, 30332
...!{akgua,allegra,amd,hplabs,ihnp4,seismo,ut-ngp}!gatech!gitpyr!kludge