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From: roy@phri.UUCP (Roy Smith)
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <2213@phri.UUCP>
Date: Sun, 16-Feb-86 10:37:39 EST
Article-I.D.: phri.2213
Posted: Sun Feb 16 10:37:39 1986
Date-Received: Tue, 18-Feb-86 04:28:03 EST
References: <946@garfield.UUCP> <3421@nsc.UUCP> <1404@gitpyr.UUCP> <175@oasys.UUCP>
Reply-To: roy@phri.UUCP (Roy Smith)
Organization: Public Health Research Inst. (NY, NY)
Lines: 24
Summary: Data General Nova had infinite indirection too

In article <175@oasys.UUCP> maa@oasys.UUCP writes:
> This computer [the GPL-3055] supported infinate inderection with indexing
> at every level.  I.e. all address had an indirect bit and index register
> number in them.

	I understand that every address in the DG Nova used one bit (the
sign bit, I guess) to indicate indirection.  The indirect addressing mode
was not decoded as part of the instruction, but as part of the address.  As
long as the address you fetched had the indirect bit set, the machine kept
doing another level of indirection.

	I think that the CPU only checked for interrupts at the completion
of an instruction.  You could generate an infinite indirection loop (two
addresses which point to each other) and there was no way to halt the CPU
short of pulling the plug.

	We had one of these in the EE lab at college, but I never actually
got a chance to play with it so I may have some details wrong.  By the time
I got my hands on it, the most valuable parts left were the rack and the
power supplies.
-- 
Roy Smith, {allegra,philabs}!phri!roy
System Administrator, Public Health Research Institute
455 First Avenue, New York, NY 10016