Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.1 6/24/83; site ubc-cs.UUCP Path: utzoo!utcsri!ubc-vision!ubc-cs!ludemann From: ludemann@ubc-cs.UUCP (Peter Ludemann) Newsgroups: net.arch Subject: Re: Addressing modes Message-ID: <169@ubc-cs.UUCP> Date: Wed, 19-Feb-86 12:03:39 EST Article-I.D.: ubc-cs.169 Posted: Wed Feb 19 12:03:39 1986 Date-Received: Wed, 19-Feb-86 14:44:34 EST References: <946@garfield.UUCP> <1417@sdcsvax.UUCP> <6777@boring.UUCP> <1433@gitpyr.UUCP> Reply-To: ludemann@ubc-cs.UUCP (Peter Ludemann) Organization: UBC Department of Computer Science, Vancouver, B.C., Canada Lines: 56 Keywords: RISC, optimiser, compiler In article <1433@gitpyr.UUCP> kludge@gitpyr.UUCP (Scott Dorsey) writes: >In article <6777@boring.UUCP> jack@mcvax.UUCP (Jack Jansen) writes: >>No, please..... The idea of a RISC architecture is to *eliminate* >>all fancies like indexed addressing. The point is, a compiler will >>have a terrible time generating code for it. ... > > That is absolutely true, but who is to say just WHAT instructions >and adressing modes are really needed... >... Without fancy register stacks, RISC machines DO tend to execute >faster than their CISC contemporaries doing most problems. Maybe this >is due to the increase in compiler simplicity, in which case the idea >would seem to me to build a compiler which can better use the CISC. > As a sometimes compiler writer who has tackled some optimisation problems, I would like to point out that compiler writing is tricky enough without complexities added by the machine's instruction set. For a description of some of the difficulties, take a look at the description of the portable C compiler in the Unix programmer's manual, volume 2 (especially the part on register allocation for expressions). Here's a simple example problem. On an IBM/360/370/..., there are two ways to generate code for "A := B[I]": LA R1,B load address of B into reg 1 A R1,I add value of I to reg 1 L R0,0(,R1) load value pointed by reg 1 into reg 0 ST R0,A store value in reg 0 into A and: LA R1,B load address of B into reg 1 L R2,I load value of I into reg 2 L R0,0(R1,R2) load value pointed by reg1 + reg2 into reg 0 ST R0,A store value in reg 0 into A (There are more possibilities, such as replacing the last two lines of the first way by "MVC A,0(R1) - move memory to memory". Also, the "A R1,I" could be done by "LA R1,I(R1)".) Now, which is the best method? In this case, the amount of code generated is almost the same but execution time will vary. In fact, what is faster on one machine model may be slower on another. A dramatic example of this was a text processing program which was sped up about 10% by replacing all MVCL (move character long) instructions by the simpler MVC (which could only do up to 256 bytes) inside a loop. But I digress. The two methods have one other difference: the first uses 2 scratch registers (1 if the MVC instruction is used) whereas the second uses 3 scratch registers. So, deciding which to use can also depend on how many scratch registers are available. As far as I'm concerned, the test for RISCness should be: given any piece of source code, is there only one reasonable code sequence which can be output by the compiler? -- -- Peter Ludemann ludemann@ubc-cs.uucp (ubc-vision!ubc-cs!ludemann) ludemann@cs.ubc.cdn (ludemann@cs.ubc.cdn@ubc.mailnet) ludemann@ubc.csnet (ludemann%ubc.csnet@CSNET-RELAY.ARPA)