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From: cmt@myrias.UUCP (Chris Thomson)
Newsgroups: net.arch,net.micro.mac,net.micro.68k
Subject: Re: timing loops
Message-ID: <222@myrias.UUCP>
Date: Sun, 23-Feb-86 20:38:45 EST
Article-I.D.: myrias.222
Posted: Sun Feb 23 20:38:45 1986
Date-Received: Mon, 24-Feb-86 01:37:15 EST
References: <156@motatl.UUCP> <530@hoptoad.uucp> <2795@amdahl.UUCP> <221@myrias.UUCP> <2817@amdahl.UUCP> <689@well.UUCP>
Organization: Myrias Research, Edmonton
Lines: 11

> >(S/370 architecturally has 244 picosecond resolution)
>    I admit to knowing little about the S/370, but a 4 GHz clock rate?

The 370 architecture has timers that are 64 bits wide, with the 12th bit
from the right (low order) end being 1 microsecond.  It is model-dependent
how many of the low-order 12 bits actually count, as opposed to holding zero
values.  However, the timer resolution should be similar to instruction
execution time, since the instruction store time of day is required to give
a different answer each time it is used, even on a multiple-CPU
configuration.  Current high-end 370 models have resolutions of a few
nanoseconds.