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From: nather@utastro.UUCP (Ed Nather)
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <400@utastro.UUCP>
Date: Fri, 21-Feb-86 17:00:18 EST
Article-I.D.: utastro.400
Posted: Fri Feb 21 17:00:18 1986
Date-Received: Mon, 24-Feb-86 05:46:50 EST
References: <187@anwar.UUCP> <1441@gitpyr.UUCP>
Organization: U. Texas, Astronomy, Austin, TX
Lines: 31
Keywords: conditionality, universal

In article <1441@gitpyr.UUCP>, kludge@gitpyr.UUCP (Scott Dorsey) writes:
> First of all, why can't a jump
> be treated as a special case of LOAD/STORE/MOVE, because most machine implement
> it that way anyway (MOV 1200, PC).  Of course, that makes conditional jumps
> impossible.  So, just set one (or two) bits of every instruction aside to make
> it possible to conditionally execute any instruction.
> 
> Scott Dorsey

Perhaps you just paste a bit from a condition flag onto the (low) end, and
then you would jump to one of two (successive) locations depending on the
condition.  The first of that pair would probably need to be an unconditional
jump in most cases, but look, Ma!  No decoding!

The LGP-30 computer had only one test instruction (test minus) and it worked,
but was a touch awkward to program a test for zero -- but it could be done.
Whether it's worth doing is another question.

The TRUE RISC would have only one instruction: subtract.  With only one
instruction, you wouldn't need an op-code field; every instruction is just
a pair of addresses (what to subtract from what).  An "add" subroutine
would need 3 instructions.  With memory-mapped I/O and the above convention
for conditional branching, you'd have it all.

TRUE RISC is not a trademark of any known company.

-- 
Ed Nather
Astronomy Dept, U of Texas @ Austin
{allegra,ihnp4}!{noao,ut-sally}!utastro!nather
nather@astro.UTEXAS.EDU