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From: martin@minster.UUCP (martin)
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <700@minster.UUCP>
Date: Fri, 21-Feb-86 08:08:46 EST
Article-I.D.: minster.700
Posted: Fri Feb 21 08:08:46 1986
Date-Received: Mon, 24-Feb-86 05:51:13 EST
References: <187@anwar.UUCP> <1441@gitpyr.UUCP>
Reply-To: martin@minster.UUCP (martin)
Organization: University of York, England
Lines: 46

In article <1441@gitpyr.UUCP> kludge@gitpyr.UUCP (Scott Dorsey) writes:
>
>impossible.  So, just set one (or two) bits of every instruction aside to make
>it possible to conditionally execute any instruction.  Is it worth the trouble

	The Acorn Risc Machine (ARM), does exactly this, although not for the
same reasons. All instructions (which are 32-bits long) have a 4-bit condition
field, and the instruction is only executed if the condition is true.
Obviously the condition 'always true' is one of the 16 possible.
	The reason for this approach is that it allows small sequences of
instructions to be skipped, without the overhead of a branch instruction, and
the associated pipeline flush. In a machine which executes instructions in
one clock cycle this can be a considerable saving.
	The ARM only has two main addressing modes, which are variations on an
indexed addressing mode, but these are associated with various options, so
that the result of the indexing operation can be written back to a register,
allowing other addressing modes (post increment etc) to be constructed.
There is also a form of immediate addressing mode.

	It is interesting to note that Acorn removed delayed branches when
virtual memory support was added to the processor, because it wasn't clear
how to restart the instruction following a branch! Perhaps some of the
other RISC machines have solved this, if they have I wonder if it was simple
enough to be worth it, or not? Does anyone know?

For more information on the ARM, I know of the following articles:
	Byte January 1986:
		"Byte U.K.: The Acorn RISC Machine"
		pp 387-393
	Electronics, August 5, 1985:
		"Acorn goes to market with RISC microprocessor"
		pp 14-15
	Electronics, August 26, 1985:
		"At 3 Mips, RISC Processor is Among Fastest Chips Around"
		pp 48-49
and for those in the UK:
	Personal Computer World (Sometime late last year!)
		"The Acorn RISC Machine" (approx)

I hope this is of interest:
		M C Atkins
usenet: ukc!minster.uucp!martin

PS.
	I have no connection with Acorn at all, except that I like the look
of the ARM!