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From: patc@tekcrl.UUCP (Pat Caudill)
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <542@tekcrl.UUCP>
Date: Sat, 22-Feb-86 09:26:40 EST
Article-I.D.: tekcrl.542
Posted: Sat Feb 22 09:26:40 1986
Date-Received: Wed, 26-Feb-86 04:28:31 EST
References: <187@anwar.UUCP>
Reply-To: patc@tekcrl.UUCP (Pat Caudill)
Organization: Tektronix, Beaverton OR
Lines: 19
Summary: Immediate Address mode in RISC.


	Under some circumstances you can get by with only register
indirect load and store and load half register immediate. The load
register to register can be done by add register to zero immediate
giving register. If the immediate is a small constant built into the
main instruction (doesn't require a second word fetch) this is a move.
Some designs also forced a register to always contain zero for
sequences like this.
	The IBM 801 allowed memory addressing only for load and store.
But it allowed 16 bit immediate operands. The instruction would
operate on either the upper or lower half of the register. At first
I thought this was a crock until I realized it didn't take any more
memory cycles than an instruction followed by a word of immediate
data. And of course it greatly simplified the instruction cycling.
And sometimes you can get away with out the second instruction.
The 801 allowed immediate operands for any of the logical instructions.
and lower half immediate on add and subtract.

			Tektronix!tekcrl!patc