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From: jlg@lanl.ARPA (Jim Giles)
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <1476@lanl.ARPA>
Date: Tue, 25-Feb-86 13:36:42 EST
Article-I.D.: lanl.1476
Posted: Tue Feb 25 13:36:42 1986
Date-Received: Wed, 26-Feb-86 06:39:44 EST
References: <946@garfield.UUCP> <1417@sdcsvax.UUCP> <6777@boring.UUCP> <1433@gitpyr.UUCP> <169@ubc-cs.UUCP> <1982@peora.UUCP>
Reply-To: jlg@a.UUCP (Jim Giles)
Organization: Los Alamos National Laboratory
Lines: 36
Keywords: RISC, optimiser, compiler

In article <1982@peora.UUCP> jer@peora.UUCP (J. Eric Roskos) writes:
>> As far as I'm concerned, the test for RISCness should be: given any piece
>> of source code, is there only one reasonable code sequence which can be
>> output by the compiler?
>
>How is that a test for "RISCness"?  Following the above scheme, you could,
>for example, have a machine that directly (and optimally) interpreted some
>concise representation of the source code... but that's exactly what people
>are calling a CISC machine, and are claiming is bad...

That's just the problem.  The designers of CISC machines think that they
are making the compiler writer's job easier by supplying opcodes to
perform high level semantics.  Unfortunately, NO ONE has yet succeeded
in developing an instruction set which can 'directly (and optimally)'
interpret the semantics of the source code.  What usually happens is
that the 'high level' instruction is not as efficient as a sequence or
loop of simpler instructions - or it is only efficient for a subset of
its possible uses. ( As an example, consider the famous case of the VAX
instruction for evaluating polynomials.  It was never as fast as a loop
of simpler code to do the same job and it was horribly inefficient in
the case where the compiler could detect a large number of zero
coefficients.)  As a result, compilers must be VERY complex to generate
good code on CISC machines.

At best, the CISC machines provide some instructions which are generally
useful as well as lots of instructions which are seldom or never used
(consider all the wierd addressing modes of modern vaxen - which most
compilers never generate).  The idea of RISC is to keep these instructions
which are generally useful, and make them as fast as possible by
eliminating all the seldom used instructions.  A useful side effect of
RISC archetecture is that it permits compiler writers to implement high
level semantics with simple 'codes skeletons' since there is usually only
one efficient sequence of code which reflects the required meaning.

J. Giles
Los Alamos