Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Path: utzoo!linus!gatech!dana From: dana@gatech.CSNET (Dana Eckart) Newsgroups: net.arch Subject: RISC question Message-ID: <2809@gatech.CSNET> Date: Mon, 24-Feb-86 15:15:04 EST Article-I.D.: gatech.2809 Posted: Mon Feb 24 15:15:04 1986 Date-Received: Wed, 26-Feb-86 07:21:50 EST Organization: School of Information and Computer Science, Georgia Tech, Atlanta Lines: 44 I have a question concerning the choice of word size in RISC machines. Namely, many seem to choose 32 bit architectures. I have done some reading on the subject and given it a fair bit of thought -- however, I can not think of a "good" reason why 24 bit architectures are not used instead. Consider the RISCI Berkeley: 7 1 8 8 8 (bits) ------------------------------------------------------- | opcode | addr mode | operand1 | operand2 | operand3 | ------------------------------------------------------- [I must admit that since the information that I was able to get from some of the published articles was not very complete, the above may not be completely accurate.] The use of 8 bits for register operands is needed to address the many registers inside of the "windows" (I guess). The alternative apporoach taken by IBM and Stanford (to use a set of "general" purpose registers) seemed to require fewer registers (16 for IBM and 32 for Stanford -- if memory serves correctly -- although I did not find any hints about the size of the instructions, perhaps they are able to get 2 instructions per word?). Furthermore it seems that using the more advanced compiler technology that was then required to get the most of the these sets of "general" purpose register sets, that these machines were comparable to that built by the Berkeley group. Thus it seems to me (naively so perhaps) that one could design a RISC to have 64 "general" purpose registers (in fact one might want to consider whether or not such a small set could also be effectively windowed I suppose), a 24 bit word (and data bus), with 32 instructions (many of the existing RISCs are very close to this) and two addressing modes (PC realative and indexed). Is there something wrong with this idea? Is my basic understanding of RISCs incorrect or misguided? Have we surrendered to 32 bits without a "good" reason? I am very curious and would appreciate any and all notes (mail or net). [I appologize to those involved if I have unwittingly misrepreseneted their work or ideas.] Thanks in advance..... --dana (dana@gatech) -- --Dana Eckart Georgia Insitute of Technology, Atlanta Georgia, 30332 ...!{akgua,allegra,amd,hplabs,ihnp4,seismo,ut-ngp}!gatech!gitpyr!dana