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Path: utzoo!linus!faron!bs
From: bs@faron.UUCP (Robert D. Silverman)
Newsgroups: net.arch
Subject: Re: RISC question
Message-ID: <487@faron.UUCP>
Date: Mon, 24-Feb-86 19:28:55 EST
Article-I.D.: faron.487
Posted: Mon Feb 24 19:28:55 1986
Date-Received: Wed, 26-Feb-86 07:26:57 EST
References: <2809@gatech.CSNET>
Organization: The MITRE Coporation, Bedford, MA
Lines: 27

> I have a question concerning the choice of word size in RISC machines.
> Namely, many seem to choose 32 bit architectures.  I have done some
> reading on the subject and given it a fair bit of thought -- however,
> I can not think of a "good" reason why 24 bit architectures are not
> used instead.  Consider the RISCI Berkeley:
> 
> 	     7         1          8          8          8   (bits)
> 	-------------------------------------------------------
> 	| opcode | addr mode | operand1 | operand2 | operand3 |
> 	-------------------------------------------------------
> 
> [I must admit that since the information that I was able to get from some 
> of the published articles was not very complete, the above may not be
> completely accurate.]  The use of 8 bits for register operands is needed to
> address the many registers inside of the "windows" (I guess).   The
> alternative apporoach taken by IBM and Stanford (to use a set of "general"
> purpose registers) seemed to require fewer registers (16 for IBM and 32
> for Stanford -- if memory serves correctly -- although I did not find any
 
etc. etc.

Some of us feel that 32 bits is not enough, especially those of us who like
to do a lot of integer arithmetic. 2^24 is not enough numerical precision for
many applications. Personally I'd settle for a 1 MIP machine with 256 bit
words and double length registers.  :-) :-)

Bob Silverman