Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!linus!philabs!cmcl2!seismo!lll-crg!lll-lcc!qantel!hplabs!pesnta!peora!jer
From: jer@peora.UUCP (J. Eric Roskos)
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <1981@peora.UUCP>
Date: Mon, 24-Feb-86 09:22:54 EST
Article-I.D.: peora.1981
Posted: Mon Feb 24 09:22:54 1986
Date-Received: Wed, 26-Feb-86 07:43:38 EST
References: <137@hhb.UUCP> <3686@utah-cs.UUCP> <15403@rochester.UUCP>
Organization: Concurrent Computer Corporation, Orlando, Fl
Lines: 17

> I suggest looking very seriously at the addressing mode provided by
> Patterson for the RISC I and RISC II chips.  The form is
>
>       value in register + constant = effective address
>
> This allows absolute addressing with a 0 valued register, register indirect
> with a 0 valued constant, and register displaced when both are non-zero.

Then, I suggest looking very seriously at the "indexed" mode of the
Motorola 6800 family, 10 years or so older than the RISC chips!

Fortunately, from the example on how to load a constant into a register
that preceeded this, I know the above comment was meant as a joke... :-)
-- 
UUCP: Ofc:  jer@peora.UUCP  Home: jer@jerpc.CCUR.UUCP  CCUR DNS: peora, pesnta
  US Mail:  MS 795; CONCURRENT Computer Corp. SDC; (A Perkin-Elmer Company)
	    2486 Sand Lake Road, Orlando, FL 32809-7642