Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Path: utzoo!linus!philabs!cmcl2!seismo!lll-crg!lll-lcc!qantel!hplabs!pesnta!peora!jer
From: jer@peora.UUCP (J. Eric Roskos)
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <1982@peora.UUCP>
Date: Mon, 24-Feb-86 09:27:29 EST
Article-I.D.: peora.1982
Posted: Mon Feb 24 09:27:29 1986
Date-Received: Wed, 26-Feb-86 07:43:53 EST
References: <946@garfield.UUCP> <1417@sdcsvax.UUCP> <6777@boring.UUCP> <1433@gitpyr.UUCP> <169@ubc-cs.UUCP>
Organization: Concurrent Computer Corporation, Orlando, Fl
Lines: 12
Keywords: RISC, optimiser, compiler

> As far as I'm concerned, the test for RISCness should be: given any piece
> of source code, is there only one reasonable code sequence which can be
> output by the compiler?

How is that a test for "RISCness"?  Following the above scheme, you could,
for example, have a machine that directly (and optimally) interpreted some
concise representation of the source code... but that's exactly what people
are calling a CISC machine, and are claiming is bad...
-- 
UUCP: Ofc:  jer@peora.UUCP  Home: jer@jerpc.CCUR.UUCP  CCUR DNS: peora, pesnta
  US Mail:  MS 795; CONCURRENT Computer Corp. SDC; (A Perkin-Elmer Company)
	    2486 Sand Lake Road, Orlando, FL 32809-7642