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From: kds@intelca.UUCP (Ken Shoemaker)
Newsgroups: net.arch
Subject: Re: RISC question
Message-ID: <219@intelca.UUCP>
Date: Mon, 24-Feb-86 18:43:25 EST
Article-I.D.: intelca.219
Posted: Mon Feb 24 18:43:25 1986
Date-Received: Wed, 26-Feb-86 21:16:51 EST
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Organization: Intel, Santa Clara, Ca.
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> >A RISC chip also makes
> >bus sharing with very high resolution displays or very high speed DMA
> >peripherals and co-processors more practical as well.
> 
> This doesn't seem right.  Does 'practical' in this sentence mean less
> bus contention?
> 
> Since a RISC machine doesn't have the fancy microcoded instructions of
> a CISC machine, it takes more instructions to do the same job.  Even

I think what could be meant is that with a smaller amount of the chip
required to be the "processor," there is more room left over to implement
such goodies as an on-chip cache, which, if large enough, will significantly
reduce the memory requirements of the processor.
-- 
If you don't like the answer, then ask another question!  Everything is the
answer to something...

Ken Shoemaker, Microprocessor Design, Intel Corp., Santa Clara, Ca.
{pur-ee,hplabs,amd,scgvaxd,dual,qantel}!intelca!kds
	
---the above views are personal.