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From: bcase@amdcad.UUCP (Brian case)
Newsgroups: net.arch
Subject: Re: RISC question
Message-ID: <9921@amdcad.UUCP>
Date: Tue, 25-Feb-86 13:07:35 EST
Article-I.D.: amdcad.9921
Posted: Tue Feb 25 13:07:35 1986
Date-Received: Fri, 28-Feb-86 04:45:14 EST
References: <2809@gatech.CSNET>
Organization: AMDCAD, Sunnyvale, CA
Lines: 17
Summary: Why 32-bit word size for RISC?

In article <2809@gatech.CSNET>, dana@gatech.CSNET (Dana Eckart) writes:
> I can not think of a "good" reason why 24 bit architectures are not
> used instead.
>                        Have we surrendered to 32 bits without a "good"
> reason?

The reason that 32-bit architectures are so popular is addressing
range:  a 32-bit address space is nice and big (for now at least)
but a 24-bit address space is too small.  Since the CPU has to
manipulate address quantities as well as loop counters and other
things, its ALU and data paths must be 32-bits wide.  Thus, even
though the 80186 can address 1 gigabyte (is that the right number?)
of virtual memory, C compilers generate bad code for large model
programs (because the CPU cannot manipulate a full address at once).
For languages like C that allow pointers to be manipulated like
data, the ALU must be able to handle a full address; the size of
the ALU determines the size of the linear address space.