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From: rmarti@sun.uucp (Bob Marti)
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <3290@sun.uucp>
Date: Tue, 25-Feb-86 12:18:45 EST
Article-I.D.: sun.3290
Posted: Tue Feb 25 12:18:45 1986
Date-Received: Fri, 28-Feb-86 07:34:31 EST
Distribution: net
Organization: Sun Microsystems, Inc.
Lines: 16

> I suggest looking very seriously at the addressing mode provided by
> Patterson for the RISC I and RISC II chips.  The form is
>
>       value in register + constant = effective address
>
> This allows absolute addressing with a 0 valued register, register indirect
> with a 0 valued constant, and register displaced when both are non-zero.

I seem to recall the CDC 6000 line had exactly this feature.  There were eight
18-bit index registers (B0 - B7) which were used by certain instructions.
The address was computed using the value in a B-register and adding a
constant.  They even had the B0 register "hardwired" to contain the value 0.

This was almost 20 years before the Berkeley people "invented" RISC ...

--Bob Marti