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From: mac@uvacs.UUCP (Alex Colvin)
Newsgroups: net.arch
Subject: Re: Re: Addressing modes
Message-ID: <222@uvacs.UUCP>
Date: Mon, 24-Feb-86 21:19:56 EST
Article-I.D.: uvacs.222
Posted: Mon Feb 24 21:19:56 1986
Date-Received: Fri, 28-Feb-86 08:11:23 EST
References: <187@anwar.UUCP> <1441@gitpyr.UUCP> <400@utastro.UUCP>
Organization: U.Va. CS dept.  Charlottesville, VA
Lines: 16

>
> The TRUE RISC would have only one instruction: subtract.  With only one
> instruction, you wouldn't need an op-code field; every instruction is just
> a pair of addresses (what to subtract from what).  An "add" subroutine
> would need 3 instructions.  With memory-mapped I/O and the above convention
> for conditional branching, you'd have it all.
> 
> TRUE RISC is not a trademark of any known company.

See the New England Digital ABLE 60 processor.  It actually has one
instruction (move).  Arithmetic is done more or less by moving to the ALU.

This processor is used for control systems, digital synthesizers
(Synklavier) and communications networks.