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Posting-Version: version B 2.10.2 GARFIELD 20/11/84; site garfield.UUCP
Path: utzoo!utcsri!ubc-vision!garfield!jeff1
From: jeff1@garfield.UUCP
Newsgroups: net.arch
Subject: Addressing modes
Message-ID: <1169@garfield.UUCP>
Date: Wed, 26-Feb-86 13:28:31 EST
Article-I.D.: garfield.1169
Posted: Wed Feb 26 13:28:31 1986
Date-Received: Sat, 1-Mar-86 07:54:48 EST
Sender: news@garfield.UUCP
Reply-To: jeff1@garfield.UUCP (Jeff Sparkes)
Organization: Memorial U. of Nfld. C.S. Dept., St. John's
Lines: 29


	It appears that most people agree on the need for immediate or
absolute addressing.  What we have (hopefully) decided on are:
	register direct
	register indirect +4 bit constant

(This is only a 16 bit machine due to size constraints.  Also, this is
only for an undergrad course in VLSI design.  Who can design something
REALLY useful in three months anyway?)

This allows us to fake immediate addressing with two instructions:
	load	Rx,PC,2
	addq	PC,1
	data
	...

Indirection is trivial.  Load the register, and then use the register for
the address.  You can do based addressing with an add instruction and an
extra register.

Branch instructions are also done neatly.  We have a mask specifiying which
condition codes to check, and then a value mask specifying the values to check 
for.  I.e if (CC & mask) == (mask & value) then branch.

It's nice to get all of these useful responses.  Thanks!

Jeff Sparkes
garfield!jeff1
jeff@garfield.mun.cdn  <- ubc-vision or ubc.csnet