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From: knudsen@ihwpt.UUCP (mike knudsen)
Newsgroups: net.arch
Subject: Re: RISC question
Message-ID: <738@ihwpt.UUCP>
Date: Fri, 28-Feb-86 15:46:43 EST
Article-I.D.: ihwpt.738
Posted: Fri Feb 28 15:46:43 1986
Date-Received: Sat, 1-Mar-86 16:33:50 EST
References: <1181@ecsvax.UUCP> <411@ccivax.UUCP> <375@ektools.UUCP>
Distribution: net
Organization: AT&T Bell Laboratories
Lines: 34

> In article <411@ccivax.UUCP> rb@ccivax.UUCP (What's in a name ?) writes:
> >A RISC chip also makes
> >bus sharing with very high resolution displays or very high speed DMA
> >peripherals and co-processors more practical as well.
> 
> This doesn't seem right.  Does 'practical' in this sentence mean less
> bus contention?
> 
> Since a RISC machine doesn't have the fancy microcoded instructions of
> a CISC machine, it takes more instructions to do the same job.  Even
> though a RISC instruction typically requires fewer bits than a CISC
> instruction, a program for a RISC machine is generally said to be
> larger than the equivalent program for a CISC machine.  With today's
> low memory prices, this is not a terrible thing.
> 
> I was always taught that 80%-95% of the bus usage of a processor was
> for instruction fetches.  Therefore if a RISC machine takes more bytes
> of instructions to run a program than a CISC machine would, the RISC
> processor will eat up MORE bus cycles, leaving fewer for displays, DMA
> , and co-processors.
> 
> John Hall
> Supervisor, Software Tools Laboratory
> Product Software Engineering
> 

I agree with you.  Modern CISC processors are microcoded
(nanocoded?) and fetch one CISC instruction from system RAM,
then proceed to fetch many nano-instrs from internal ROM
to perform it.  Meanwhile, the bus is free.
RISC machines essentially run "nano code" out of YOUR main
RAM over YOUR bus.  So yes, you seem right to me.
	mike k
Or are we both missing something?