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From: mash@mips.UUCP (John Mashey)
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <364@mips.UUCP>
Date: Fri, 28-Feb-86 00:46:02 EST
Article-I.D.: mips.364
Posted: Fri Feb 28 00:46:02 1986
Date-Received: Sat, 1-Mar-86 18:33:10 EST
References: <187@anwar.UUCP> <542@tekcrl.UUCP>
Organization: MIPS Computer Systems, Mountain View, CA
Lines: 61

Pat Caudill, Tektronix!tekcrl!patc writes:
> 	Under some circumstances you can get by with only register
> indirect load and store and load half register immediate....
> 	The IBM 801 allowed memory addressing only for load and store.
> But it allowed 16 bit immediate operands. The instruction would
> operate on either the upper or lower half of the register. At first
> I thought this was a crock until I realized it didn't take any more
> memory cycles than an instruction followed by a word of immediate
> data. And of course it greatly simplified the instruction cycling.

1) Yes, it looks like a crock, but it works.  Sneaky compilers can even
do things like keeping the upper-half of an address around in a register
for a while, thus lessening the number of fetches.

2) On this whole business of addressing modes [I'm just catching up,
since we moved buildings and were out of touch]: I recommend:
	A Characterization of Processor Performance in the VAX 11/780,
	Joel S. Emer, Douglas W. Clark, both of DEC
	Proc. 11th Ann. SYmp. on Computer Architecture (Ann Arbor, Mich,
	June 5-7), IEEE, N.Y., 301-310.
These guys have done a number of excellent studies of real VAX characteristics,
and even better, have published them.  I urge people who argue the merits
of architectural features to look up some of these papers.  For example,
see Table 4 in the above paper, from which a few columns are excerpted below:

Operand specifier distribution: (total)

Register	R	41.0%  ==> 41.0%

Short literal 	#n	15.8%
Immediate	(PC)+	 2.4%	==> 18.2%

Displacement	D(R)	25.0%
Reg.Deferred	(R)	 9.2%
Auto-inc	(R)+	 2.1%
Disp. Deferred	@D(R)	 2.7%
Absolute	@(PC)+	 0.6%
Auto-inc-deferr	@(R)+	 0.3%
Auto-dec	-(R)	 0.9%
			-----
			40.8%

What does this tell you?
1) registers get used (41%).
2) so do literals (15.8% + 2.4% = 18.2%)
3) Of the modes that actually reference memory, 83% ((25.0+9.2)/40.8) are
of the form D(R) or (R) (and the latter, or course is 0(R)).

Note: don't read TOO much into these figures, but it is interesting to
see how little dynamic count is contributed by some of the lesser-used modes.
Again, I recommend this paper highly.  Among other things, it has a good
analysis of average VAX instruction timing, showing that the "average"
VAX instruction uses 10.6 200ns cycles, i.e.:
	A "1-MIP" 11/780 IS REALLY A HALF-VAX-MIP CPU!
(This is why we always talk in performance realtive to VAXen, counting
Mips only confuses you.)
-- 
-john mashey
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