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From: hammond@petrus.UUCP (Rich A. Hammond)
Newsgroups: net.arch
Subject: Re: RISC vs INTEL
Message-ID: <41@petrus.UUCP>
Date: Mon, 3-Mar-86 07:13:30 EST
Article-I.D.: petrus.41
Posted: Mon Mar  3 07:13:30 1986
Date-Received: Tue, 4-Mar-86 02:31:13 EST
References: <117@pyramid.UUCP>
Distribution: net
Organization: Bell Communications Research, Inc
Lines: 33

> clif@intelca.UUCP (Clif Purkiser) writes:
> 
> >The RISC machine I designed for my Computer Architecture course ...
to which sun!pyramid!dan responds:
> ...  Yes, there are
> RISC machines that have some multiple cycle instructions.  In my experience,
> though, something like a block move can usually be implemented with a loop
> (especially using an efficient branch scheme) of simpler instructions with
> *no loss of performance*.
> 
*NO LOSS OF PERFORMANCE?!?  No way!  Look, a memory block move is a RISC
at its worst, since the block move defeats the data cache.  A M68000
(16 bit data and instruction bus) is FASTER than the UCB RISC (32 bit
data and instruction bus) for equivalent 32 bit at a time block moves.
Even if the RISC instructions are in a cache, the data isn't and what's
worse, every other data access is a write.  Essentially, the block transfer
measures data bus bandwidth, not cache bandwidth, which is what RISCs
exploit.

Be careful when comparing "clock ticks".  No RISC I've
seen written up actually finishes instructions in ONE cycle, but since
the RISC is pipelined, an instruction completes every cycle.  There
is a difference!

Second, the 68000 family and Intel's *86 family tend to have high
frequency clocks divided on chip for micro-cycle timing.  RISC chips
often have much slower clocks, sometimes with separate phases 
generated off chip, what you need to use is the clock rate which
allows the chips to run with a constant speed mmain memory.
I.e. the time from address valid until data returns through the
buffers to the CPU should be the same, then calculate what clock rate
the CPU uses to have that time be the maximum memory cycle time.
Rich Hammond	{allegra, ucbvax,decvax} !bellcore!hammond