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From: aglew@ccvaxa.UUCP
Newsgroups: net.arch
Subject: Re: RISC question
Message-ID: <5100015@ccvaxa>
Date: Sat, 1-Mar-86 18:10:00 EST
Article-I.D.: ccvaxa.5100015
Posted: Sat Mar  1 18:10:00 1986
Date-Received: Tue, 4-Mar-86 04:48:33 EST
References: <2809@gatech.CSNET>
Lines: 39
Nf-ID: #R:gatech.CSNET:2809:ccvaxa:5100015:000:2014
Nf-From: ccvaxa.UUCP!aglew    Mar  1 17:10:00 1986


>/* Written  2:46 pm  Feb 28, 1986 by knudsen@ihwpt.UUCP in ccvaxa:net.arch */
>I agree with you.  Modern CISC processors are microcoded
>(nanocoded?) and fetch one CISC instruction from system RAM,
>then proceed to fetch many nano-instrs from internal ROM
>to perform it.  Meanwhile, the bus is free.
>RISC machines essentially run "nano code" out of YOUR main
>RAM over YOUR bus.  So yes, you seem right to me.
>	mike k
>Or are we both missing something?

The problem is, most of the microcoded instructions that keep the CISC off the
bus can be executed in one cycle, so all those extra micro-cycles are useless,
and only go to support uncommon multicycle instructions.

The biggest use of microcode is in implementing complicated addressing modes
(I believe that RISCs should rather be called RAMMs - Reduced Addressing 
Mode Machines). Indexed address calculations can be implemented in the cycle
that sets up to get data from memory; indirect addressing requires an extra
memory access, so there goes the advantage of keeping the CISC off the bus.

What about other CISC instructions? Queue insertion, translate tables, etc
- all require lots of memory accesses, so the bus contention argument doesn't
hold.

The only microcoded instructions that truly reduce bus contention are compute
intensive operations like multiply and divide, and possibly multi-bit shifts
if you are foolish enough not to want a barrell shifter. Unfortunately,
simple operations like add and subtract are much more common.

Can anyone think of any more complicated instructions that would have to be
done in microcode that would not require constantly going back to memory for
data?

Well, where CISC operations can't reduce bus contention overmuch, RISCs can
take two steps to reduce it: (1) by providing a lot of registers, most scalar
(and in some architectures, vector (the Cray is really just a big RISC))
data can be accessed without going to memory; and, (2) you can spend time
and money on providing good instruction caches.