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From: dan@pyramid.UUCP (Danial Carl Sobotta)
Newsgroups: net.arch
Subject: RISC cache vs CISC u-code
Message-ID: <136@pyramid.UUCP>
Date: Mon, 3-Mar-86 20:54:08 EST
Article-I.D.: pyramid.136
Posted: Mon Mar  3 20:54:08 1986
Date-Received: Wed, 5-Mar-86 05:46:34 EST
Reply-To: dan@.UUCP (Dan Sobottka)
Organization: Pyramid Technology Corp., Mountain View, CA
Lines: 46


> This doesn't seem right.  Does 'practical' in this sentence mean less
> bus contention?
> 
> Since a RISC machine doesn't have the fancy microcoded instructions of
> a CISC machine, it takes more instructions to do the same job.  Even
> though a RISC instruction typically requires fewer bits than a CISC
> instruction, a program for a RISC machine is generally said to be
> larger than the equivalent program for a CISC machine.  With today's
> low memory prices, this is not a terrible thing.
> 
> I was always taught that 80%-95% of the bus usage of a processor was
> for instruction fetches.  Therefore if a RISC machine takes more bytes
> of instructions to run a program than a CISC machine would, the RISC
> processor will eat up MORE bus cycles, leaving fewer for displays, DMA
> , and co-processors.

knudsen@ihwpt.UUCP (mike knudsen) replys:

>I agree with you.  Modern CISC processors are microcoded
>(nanocoded?) and fetch one CISC instruction from system RAM,
>then proceed to fetch many nano-instrs from internal ROM
>to perform it.  Meanwhile, the bus is free.
>RISC machines essentially run "nano code" out of YOUR main
>RAM over YOUR bus.  So yes, you seem right to me.
>Or are we both missing something?

Yup, you probably are.  The space that is freed up on a RISC chip by having
little if any u-code ROM can be used for more cache.  The (*rare*) cases
of needing a multiple RISC instruction routine to 'emulate' a CISC
instruction can be handled by having that routine in cache.  This is
automatically done by caching algorithms in hardware (simple!).
So, having the cache effectively reduces Bus traffic not only to a CISC
level (because of above explanation) but also probably LESS traffic because
the cache can be used for ALL instructions (and data).
Or am I missing something?



-- 


  'Out of the inkwell comes Bozo the Clown ...'
 
DISCLAIMER:  These opinions are neither mine nor my C-compiler's
       sun!pyramid!dan