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From: prl@ethz.UUCP (Peter Lamb)
Newsgroups: net.arch
Subject: Re: Re: Addressing modes
Message-ID: <307@ethz.UUCP>
Date: Mon, 3-Mar-86 19:11:20 EST
Article-I.D.: ethz.307
Posted: Mon Mar  3 19:11:20 1986
Date-Received: Wed, 5-Mar-86 05:52:24 EST
References: <187@anwar.UUCP> <1441@gitpyr.UUCP> <890@umn-cs.UUCP> <1468@gitpyr.UUCP>
Reply-To: prl@ethz.UUCP (Peter Lamb)
Organization: CS Department, ETH Zuerich, Switzerland
Lines: 65

In article <1468@gitpyr.UUCP> kludge@gitpyr.UUCP (Scott Dorsey) writes:
>I wouldn't call the PDP-8 a RISC machine, but then, what do you call a machine
>that can't add?

Now that just isn't true: the PDP-8 _did_ have an add instruction.
What it was missing was any LOAD instruction (no this is not a joke).

For those who have never seen a PDP-8 instruction set, here it is
(I'm doing this because I think that the '8 _was_ as RISC, though
the motivations for their design choices seem to be different:
this shouldn't surprise anyone, since the first '8s were implemented
with discrete transistors - that meant that ALU's and registers were
_expensive_)

Anyway, the 8 had a 3-bit opcode, 6 memory reference instructions
and the other 2 opcodes were used for register operate and IO,
where for these two instructions the rest of the bits described what the
instruction actually did.
Remaining were 9 bits (12-bit word), 1 indirect bit, 1 base page/current page
bit and 7 address bits. Fixed 128-word pages, none of your fancy PC-relative
stuff - that would have required another _expensive_ adder, or extra cpu
cycles.

The instructions were, then (some of the opcode names may be wrong,
it's been a long time...):
	TAD		Two's Complement Add ((acc) <- acc+(EA))
	SCA		Store and Clear Accumulator ((EA)<-(acc), (acc)<-0)
	ANA		And Accumulator ((acc)<-(EA)&(acc))
	ISZ		Increment & Skip on Zero ((EA)<-(EA)+1, skip if zero)
	JMP		Jump (PC)<-EA
	JSR		Jump to (EA)<-(PC),(PC)<-EA+1

The accumulator operate instructions could do two accumulator
operations in one instruction: one subset in the first clock cycle
of the instr, another in the next; generally they were arranged
sensibly, for example CMA (complement accumulator) was a cycle 1
opcode, and INC a cycle 2 opcode, so that negate could be done in one
instruction. There were also opcodes for shift, rotate, and conditional
skip.
Autoincrement indirection was also there (but not as opcode bits)
there were these locations in low memory, which, when addressed
indirectly, incremented themselves (shudder.....).

Anyway, given the aim of producing a minimum cost machine on the
available technology, I think that the PDP-8 was an _extremely good_
machine (fire-proof overalls on). I have heard one rumor that
the '8 was the first CPU to be sold for under $US10000, then later the
first under $US1000. In its time, it was very popular indeed, and
until reasonably recently (order mid-late 1970's) there were still
uProc versions of the 8 inside DEC products.

The important thing, in this discussion, though, was that
some similar philosophy was at work - the instruction set was
stripped down to a bare minimum, here to simplify hardware to
reduce cost by reducing the device count, in modern RISC,
to reduce design time/(individual) instruction execution time.
But both with the aim (and in the case of the '8 sucessfully)
of getting better cost-performance.

Mind you, I wouldn't want to program one in assembler though :-) .
-- 
Peter Lamb	({seismo|decvax}!mcvax!cernvax!ethz!prl)
Institut fur Informatik
ETH-Zentrum
8092 Zurich