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From: mark@mips.UUCP (Mark G. Johnson)
Newsgroups: net.arch
Subject: Re: Re: Bad devices (timing loops)
Message-ID: <374@mips.UUCP>
Date: Tue, 4-Mar-86 14:35:34 EST
Article-I.D.: mips.374
Posted: Tue Mar  4 14:35:34 1986
Date-Received: Fri, 7-Mar-86 04:58:41 EST
Distribution: net
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 26

123
In article <10040@amdcad.UUCP>   phil@amdcad.UUCP (Phil Ngai)  writes:

 > .....
 > As a matter of fact, most chips don't tell you when they are
 > ready.  When was the last time a RAM chip told you it was ready
 > for CAS after you sent RAS, or even when read data is valid?
                                  ^^^^ ^^^^ ^^^^ ^^^^ ^^ ^^^^^^

Actually, RAM chips with this feature were built ten years ago....
by AMD-Sunnyvale (Mr. Ngai's employer).  Self-timed access cycles
were accomplished by providing an "MS" output pin on the RAM,
which signaled cycle-is-done.  This allowed simple handshake
protocols, as outlined in the reference below:

ref: Jeffrey M. Schlageter, Nagab Jayakunar, Joseph H. Kroeger,
     and Vahe Sarkissian, Advanced Micro Devices, Sunnyvale, CA,
     "A 4K Static 5-V RAM", Paper THPM-12.5, International Solid-
     State Circuits Conference, Digest of Technical Papers,
     February 19-21, 1976, pp. 132-7.

-- 
-Mark Johnson
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