Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site decwrl.DEC.COM Path: utzoo!watmath!clyde!burl!ulysses!bellcore!decvax!decwrl!paulr From: paulr@decwrl.DEC.COM (Paul Richardson) Newsgroups: net.arch Subject: risc questions Message-ID: <1511@decwrl.DEC.COM> Date: Tue, 4-Mar-86 23:40:55 EST Article-I.D.: decwrl.1511 Posted: Tue Mar 4 23:40:55 1986 Date-Received: Fri, 7-Mar-86 05:48:03 EST Reply-To: paulr@decwrl.UUCP (Paul Richardson) Followup-To: no follow up Distribution: net.arch Organization: Digital Equipment Corporation Lines: 8 Keywords: Risc,cache,performance Summary: what do separate instruction and data caches buy us Has anyone taken data as to the performance gains/losses attributed to separate data/instruction caches in processors.You can reply to me at the above address,or to the net,but i am interested in info Paul Richardson