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From: kludge@gitpyr.UUCP (Scott Dorsey)
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <1505@gitpyr.UUCP>
Date: Thu, 6-Mar-86 16:08:23 EST
Article-I.D.: gitpyr.1505
Posted: Thu Mar  6 16:08:23 1986
Date-Received: Fri, 7-Mar-86 07:26:04 EST
References: <1169@garfield.UUCP> <5100016@ccvaxa>
Reply-To: kludge@gitpyr.UUCP (Scott Dorsey)
Organization: Georgia College Of Universal Knowledge
Lines: 33

In article <5100016@ccvaxa> aglew@ccvaxa.UUCP writes:
>4 bit constants hold only 20% of the offsets you're going to want, without
>scaling, and only 30% with. These numbers are preliminary results of a
>study I'm making. The distribution of the size of addressing constants
>falls off roughly exponentially, with a 50% mark at 6 bits, and an 85% mark
>at 8 bits.
>
>What I'm trying to say is, you'll get much much better results if you provide
>just a few more bits in the constant.

     Personally, as an assembly hacker, I'd love a larger constant.  The
question is if it is worth the increase in power to increase the actual
size, versus the cost of the larger field (decrease in number of other
instructions able to be decoded.  No flames from RISC advocates, please).
An 8-bit constant would certainly be valuable, especially for character 
manipulation work.  Unless you already had hardware onboard to break up
5/6/7 bit fields, these would be hard to work with, however.  Would it
be worth the extra stuff?  Would it be better to just design the 5/6/7
bit decoding into the instruction set properly?  I don't know... but
I enjoy the 32032, and would give up many things to have even a four 
bit field on the machinses I am programming today.

------
Disclaimer: Everything I say is probably a trademark of someone.  But
            don't worry, I probably don't know what I'm talking about.

Scott Dorsey
Kaptain_kludge
ICS Programming Lab, Rich 110,
Georgia Institute of Technology, Atlanta, Georgia 30332
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USnail:  Box 36681, Atlanta GA. 30332