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From: mat@amdahl.UUCP (Mike Taylor)
Newsgroups: net.arch
Subject: Re: IBM 370 TOD clock resolution
Message-ID: <2879@amdahl.UUCP>
Date: Wed, 5-Mar-86 12:05:22 EST
Article-I.D.: amdahl.2879
Posted: Wed Mar  5 12:05:22 1986
Date-Received: Fri, 7-Mar-86 07:39:26 EST
References: <561@hoptoad.uucp> <5058@alice.uUCp> <368@mips.UUCP>
Organization: Amdahl Corp, Sunnyvale CA
Lines: 26

In article <368@mips.UUCP>, kim@mips.UUCP (Kim DeVaughn) writes:
> 
> Note that bit-positions 52-63 cannot be used for timing purposes, but
> may be used for "sequencing" purposes.
> 

I know this is a nit, but that is not quite true.  It is model-dependent
which bit (if any) to the right of bit 51 is incremented for timing
purposes. The TOD clock resolution is expected to be similar to the
instruction time. On a model with 10 us. instruction time, it would be
OK to have a lower resolution, but the time value would be set as if bit
51 were being incremented every microsecond. Zeros must be set to the
right of the lowest incremented bit on UP versions. Therefore, a UP
(such as the 470 V/6) has no choice but to block until the clock "ticks"
in order to guarantee a different value for the STCK. The choice of the
minimum resolution (1 us.) means a delay of up to 1 us. An implementor
may choose a higher resolution to alleviate this problem, however, the
higher resolution must be "correct," in the sense that you can't stuff
arbitrary bits on a UP and you can use the higher resolution for timing
purposes.

Reference "S/370XA Principles of Operation" pp.4-18,4-20.
-- 
Mike Taylor                        ...!{ihnp4,hplabs,amd,sun}!amdahl!mat

[ This may not reflect my opinion, let alone anyone else's.  ]