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From: andrew@aimmi.UUCP (Andrew Stewart)
Newsgroups: net.arch,net.micro.mac,net.micro.68k
Subject: Re: timing loops
Message-ID: <728@aimmi.UUCP>
Date: Fri, 21-Feb-86 05:55:32 EST
Article-I.D.: aimmi.728
Posted: Fri Feb 21 05:55:32 1986
Date-Received: Wed, 26-Feb-86 07:25:39 EST
References: <156@motatl.UUCP> <530@hoptoad.uucp> <2795@amdahl.UUCP>
Reply-To: andrew@aimmi.UUCP (Andrew Stewart)
Organization: Heriot-Watt/Strathclyde Alvey MMI Unit, Scotland
Lines: 22
Xref: linus net.arch:2410 net.micro.mac:4830 net.micro.68k:1451

In article <2795@amdahl.UUCP> mat@amdahl.UUCP writes:

>In article <530@hoptoad.uucp>, gnu@hoptoad.uucp (John Gilmore) writes:
>> E.g. in meeting the recovery time of a particularly good USART chip
>> with a horrible bus interface, the Z8530, you need to wait 2.2us
>> between writes to it.  Give me a good way to wait 2.2us *without*
>> depending on instruction timing, and I'll consider your request.
>
>Well, on a *real* computer, you just set the TOD clock comparator for
>now+2.2 us. and go do something useful while you wait.  Sorry, couldn't
>resist.
>

On a *real* computer, you use the front panel keys. USARTS??? TOD clock???
Ha! (Remember the PDP-8, only bigger and better...)

	Andrew Stewart
-- 
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Andrew Stewart		 USENET:   ...!mcvax!ukc!aimmi!andrew

"My axioms just fell into a Klein bottle"