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From: bmw@aesat.UUCP (Bruce Walker)
Newsgroups: net.arch,net.micro.mac,net.micro.68k
Subject: Re: timing loops
Message-ID: <560@aesat.UUCP>
Date: Mon, 17-Feb-86 08:14:17 EST
Article-I.D.: aesat.560
Posted: Mon Feb 17 08:14:17 1986
Date-Received: Mon, 17-Feb-86 08:13:49 EST
References: <156@motatl.UUCP> <530@hoptoad.uucp>
Reply-To: bmw@aesat.UUCP (Bruce Walker)
Organization: AES Data Inc., Mississauga Ont., Canada
Lines: 25

>.... in meeting the recovery time of a particularly good USART chip
>with a horrible bus interface, the Z8530, you need to wait 2.2us
>between writes to it.  Give me a good way to wait 2.2us *without*
>depending on instruction timing, and I'll consider your request.
>
>PS:  if your answer is "add more chips", a lot of people will cheap
>out and use "free" software timing loops.
>-- 
>John Gilmore  {sun,ptsfa,lll-crg,ihnp4}!hoptoad!gnu   jgilmore@lll-crg.arpa

You must be clocking your 8530 at 3 MHz.  The spec for Valid Access
Recovery Time is 6TcPC+200 (nS (130 for the 'A' part)) where TcPC is
the bus clock cycle time.  At 4MHz you should wait a minimum of 1.7uS
and at 6MHz you only need to wait 1.2uS.

The kind of people that "cheap out" are the kind of people that cripple
their machines in a multitude of other subtle ways which are only
appropriate for closed-architecture "games machines".  Designers who
are creating machines with a future growth path would put in the extra
hardware (which only amounts to a small, registered PAL anyway).

Bruce Walker     {allegra,ihnp4,linus,decvax}!utzoo!aesat!bmw

"I'd feel a lot worse if I wasn't so heavily sedated." -- Spinal Tap