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From: jack@boring.UUCP
Newsgroups: net.arch,net.micro.mac,net.micro.68k
Subject: Re: timing loops
Message-ID: <6780@boring.UUCP>
Date: Mon, 17-Feb-86 08:39:43 EST
Article-I.D.: boring.6780
Posted: Mon Feb 17 08:39:43 1986
Date-Received: Wed, 19-Feb-86 01:01:58 EST
References: <156@motatl.UUCP> <530@hoptoad.uucp>
Reply-To: jack@mcvax.UUCP (Jack Jansen)
Organization: AMOEBA project, CWI, Amsterdam
Lines: 15
Xref: watmath net.arch:2552 net.micro.mac:4716 net.micro.68k:1494
Apparently-To: rnews@mcvax

>
>E.g. in meeting the recovery time of a particularly good USART chip
>with a horrible bus interface, the Z8530, you need to wait 2.2us
>between writes to it.  Give me a good way to wait 2.2us *without*
>depending on instruction timing, and I'll consider your request.

Sorry, but this bad makes it a particularly *bad* USART chip, regardless
of any other features.
Imagine writing a device driver for it, finding out that the C compiler
generates such code that there's far more than 2.2us between writes, and
leaving the place. Then, two years later, the site gets a new C compiler
with a much better optimizer..........
-- 
	Jack Jansen, jack@mcvax.UUCP
	The shell is my oyster.