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From: jdz@wucec2.UUCP
Newsgroups: net.arch
Subject: Re: Re: Addressing modes
Message-ID: <1441@wucec2.UUCP>
Date: Wed, 5-Mar-86 13:15:59 EST
Article-I.D.: wucec2.1441
Posted: Wed Mar  5 13:15:59 1986
Date-Received: Sat, 8-Mar-86 03:30:27 EST
References: <187@anwar.UUCP> <1441@gitpyr.UUCP> <400@utastro.UUCP> <222@uvacs.UUCP>
Reply-To: jdz@wucec2.UUCP (Jason D. Zions)
Organization: Wash. U. Center for Engineering Computing
Lines: 31

> The TRUE RISC would have only one instruction: subtract.  With only one
> instruction, you wouldn't need an op-code field; every instruction is just
> a pair of addresses (what to subtract from what).  An "add" subroutine
> would need 3 instructions.  With memory-mapped I/O and the above convention
> for conditional branching, you'd have it all.

Not quite. You need two address, you see. If we go to two instructions, we
can get away with only one address. To wit:

	SUBS X	Subtract cotents of location X from accumulator and
		store results in accumulator and in X

	JUMP X	Indirect jump; i.e. PC <= contents of location X

Proving this beast to be functionally complete is arduous but do-able.
We use it as an exercise in our Computer Architecture class. The machine is
called the TWINC, for TWo INstruction Computer. We have surmised the existence
of an OINC, but have not successfully proved functional completeness (the
conditional branch is usually the problem). You describe OINC with two addr. -
can you do it with only one?

One student did a VLSI design of the TWINC for LSI design class; we're thinking
about fabrication by MOSIS. Only did an 8 bit word, though.

I don't have the cotext for the comment about "the above convention for
conditional branching" - could someone mail it to me?
-- 
Jason D. Zions			...!{seismo,cbosgd,ihnp4}!wucs!wucec2!jdz
Box 1045 Washington University
St. Louis MO 63130  USA		(314) 889-6160
Nope, I didn't say nothing. Just random noise.