Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP
Posting-Version: version B 2.10.1 6/24/83; site mmintl.UUCP
Path: utzoo!watmath!clyde!burl!ulysses!bellcore!decvax!linus!philabs!pwa-b!mmintl!franka
From: franka@mmintl.UUCP (Frank Adams)
Newsgroups: net.arch,net.micro.mac,net.micro.68k
Subject: Re: timing loops
Message-ID: <1162@mmintl.UUCP>
Date: Tue, 4-Mar-86 15:08:32 EST
Article-I.D.: mmintl.1162
Posted: Tue Mar  4 15:08:32 1986
Date-Received: Sat, 8-Mar-86 21:00:58 EST
References: <156@motatl.UUCP> <530@hoptoad.uucp> <6780@boring.UUCP>
Reply-To: franka@mmintl.UUCP (Frank Adams)
Organization: Multimate International, E. Hartford, CT
Lines: 14
Xref: watmath net.arch:2724 net.micro.mac:5008 net.micro.68k:1548

In article <6780@boring.UUCP> jack@mcvax.UUCP (Jack Jansen) writes:
>>E.g. in meeting the recovery time of a particularly good USART chip
>>with a horrible bus interface, the Z8530, you need to wait 2.2us
>>between writes to it.
>
>Sorry, but this bad makes it a particularly *bad* USART chip, regardless
>of any other features.

It seems to me that from theoretical considerations, there will always be
*some* time dependencies in any device.  If you run it with a fast enough
processor, it will stop working.

Frank Adams                           ihnp4!philabs!pwa-b!mmintl!franka
Multimate International    52 Oakland Ave North    E. Hartford, CT 06108