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Path: utzoo!watmath!clyde!burl!ulysses!bellcore!decvax!linus!philabs!pwa-b!mmintl!franka
From: franka@mmintl.UUCP (Frank Adams)
Newsgroups: net.arch
Subject: Re: Addressing modes
Message-ID: <1163@mmintl.UUCP>
Date: Tue, 4-Mar-86 15:50:24 EST
Article-I.D.: mmintl.1163
Posted: Tue Mar  4 15:50:24 1986
Date-Received: Sat, 8-Mar-86 21:01:30 EST
References: <946@garfield.UUCP> <1417@sdcsvax.UUCP> <6777@boring.UUCP> <1433@gitpyr.UUCP> <169@ubc-cs.UUCP>
Reply-To: franka@mmintl.UUCP (Frank Adams)
Organization: Multimate International, E. Hartford, CT
Lines: 24
Keywords: RISC, optimiser, compiler

In article <169@ubc-cs.UUCP> ludemann@ubc-cs.UUCP (Peter Ludemann) writes:
>As far as I'm concerned, the test for RISCness should be: given any
>piece of source code, is there only one reasonable code sequence which can be
>output by the compiler?

This is not a possible objective.  Consider sequences like:

   A = B[I];
   C = D[I];

On any machine which has registers, it is possible to do this by loading I
into a register, doing an address calculation for B[I] (which may be combined
with the next instruction), and moving the value of B[I] to A (perhaps via a
register).  One can then perform the same calculation for the second
statement.  Alternatively, one can keep the value of I (possibly shifted) in
a register after the first statement, and use it again in the second.

Either of these is a reasonable code sequence to be generated; it depends on
how much optimization you want to do.  This is only one simple example; there
are arbitrarily complex ones.  The problem of code optimization is
undecidable in general.

Frank Adams                           ihnp4!philabs!pwa-b!mmintl!franka
Multimate International    52 Oakland Ave North    E. Hartford, CT 06108