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From: jlg@lanl.UUCP
Newsgroups: net.arch
Subject: Re: Addressing modes (really VAX polyd instruction)
Message-ID: <104@lanl.ARPA>
Date: Wed, 5-Mar-86 13:10:29 EST
Article-I.D.: lanl.104
Posted: Wed Mar  5 13:10:29 1986
Date-Received: Sat, 8-Mar-86 23:21:13 EST
References: <946@garfield.UUCP> <1417@sdcsvax.UUCP> <6777@boring.UUCP> <1476@lanl.ARPA> <78@cad.UUCP>
Reply-To: jlg@a.UUCP (Jim Giles)
Organization: Los Alamos National Laboratory
Lines: 24
Keywords: RISC, optimiser, compiler

In article <78@cad.UUCP> rudell@cad.UUCP (Richard Rudell) writes:
...
>Lastly, I will not comment on the difficulty of a compiler generating
>code for an instruction which changes 6 of the 16 general purpose
>registers.
>
>My only point is that the VAX polyd instruction is FASTER than the best
>one can do in VAX assembler given all nonzero coefficients.  Period.
>So why is the VAX poly instruction so famous ?

You would have convinced me if the benchmarks you did had included the
necessary set-up code for each different possible coding, as well as
use in a real code where register scheduling conflicts must be weighed
in the balance.  I didn't claim that the individual instruction was always
less efficient (maybe I sould have phrased differently). Sometimes it
is less efficient, but the hardware types wouldn't have provided it
if its failings were really obvious.  The problem is that the instruction
requires extra set-up that ordinary code sequences don't, and (as you say)
uses up 6 registers.  Since your benchmark doesn't include timing of
these in a real code environment, it doesn't really measure the speed
of the instruction.

J. Giles
Los Alamos