Relay-Version: version B 2.10 5/3/83; site utzoo.UUCP Posting-Version: version B 2.10.2 9/18/84; site peora.UUCP Path: utzoo!watmath!clyde!burl!ulysses!mhuxr!mhuxt!houxm!hjuxa!petsd!peora!jer From: jer@peora.UUCP (J. Eric Roskos) Newsgroups: net.arch Subject: Re: PDP-8 Message-ID: <2007@peora.UUCP> Date: Sat, 8-Mar-86 01:18:04 EST Article-I.D.: peora.2007 Posted: Sat Mar 8 01:18:04 1986 Date-Received: Sun, 9-Mar-86 00:16:43 EST References: <187@anwar.UUCP> <1441@gitpyr.UUCP> <890@umn-cs.UUCP> <1468@gitpyr.UUCP> <307@ethz.UUCP> Organization: Concurrent Computer Corporation, Orlando, Fl Lines: 120 This posting brought back many fond memories; the first machine I ever did any systems programming on was a PDP-8, and as an undergraduate I spent many hours disassembling a very primitive OS that ran on that machine in order to learn how it worked. (I was thinking the other day that I wished I had one of them now, in fact, just for sentimental reasons!) As the person who wrote the original posting mentioned, the mnemonics he gave were somewhat different from the real ones; the real mnemonics for the five memory reference instructions were AND, TAD, ISZ, DCA, and JMS. (The DCA [deposit and clear accumulator] is, incidentally, quite valuable for obscure theoretical reasons.) One thing the poster left out (or didn't mention in detail, anyway) was the two "augmented instructions" of the PDP-8. The first of these, the "IOT" instruction, did I/O operations; the first 3 bits of the instruction were an octal 6, the next six bits identified the device on which the operation was to be performed, and the last 3 bits identified the operation to be performed on the device. (Actually the low-order 9 bits were broadcast to all devices; the device whose ID matched was supposed to accept and act upon the low-order 3 bits. In those days I didn't know anything about how the hardware worked, so I don't know what the device did then, but it could apparently read and write the accumulator in response to this instruction.) The other augmented instruction was called "The Operate Instruction", and consisted of three groups of "microinstructions". Group 1 performed logical operations on the accumulator; group 2 did tests which conditionally skipped the next instruction based on the value of the accumulator, and group 3 worked on the "multiplier quotient" register. (Group 1 and 2 also operated on the "link bit", which was essentially a carry bit out of the adder, although it was often used as a flag bit since there were instructions to explicitly set and clear it.) Here are the operate group 1 microinstructions: NOP 7000 No operation. Caused a 1-cycle delay. IAC 7001 Increment accumulator. BSW 7002 Byte swap (on a 6-bit byte). RAL 7004 Rotate accumulator left. RTL 7006 Rotate two left. RAR 7010 Rotate accumulator right. RTR 7012 Rotate two right. CML 7020 Complement link. CMA 7040 Complement accumulator. CLL 7100 Clear Link. CLA 7200 Clear accumulator. Notice that, except for RAR, RAL, RTR, RTL, and BSW, each of these operations is represented by a distinct bit in the instruction word. These were called "microinstructions" because you could combine more than one of these operations into one instruction by virtue of this fact. There were four commonly-used combinations that had their own mnemonics: CIA 7041 Complement and Increment Accumulator. STL 7120 Set the link (actually clear and complement link). STA 7240 Set the accumulator (actually CLA and CMA). GLK 7204 Get the Link (actually CLA and RAL). The second group of "microinstructions" was even better bit-encoded. The high-order 4 bits of these instructions all had 1s; the remaining bits were as follows (numbering from the left): 4 - clear accumulator 5 - skip on minus accumulator 6 - skip on zero accumulator 7 - skip on non-zero link 8 - reverse skip sense of bits 5, 6, and 7 9 - or switch register (on front panel) into accumulator 10 - halt 11 - always zero If more than one bit was set, the skips were done first, followed by the clear-accumulator (CLA) (since otherwise the accumulator would be cleared before it was tested), followed by the OSR or HLT. There were ten mnemonics that were combinations of the above (which you can figure out easily from the above): HLT, OSR, SKP, SNL, SZL, SZA, SNA, SMA, SPA, and CLA. You could also combine several of the skip instructions into one; the following were legal: SZA SNL SNA SZL SMA SNL SPA SZL SMA SZA SPA SNA SMA SZA SNL SPA SNA SZL And, finally, there were the "group 3 operate microinstructions"; however, they were used mostly for the KE8 Extended Arithmetic Element, which we didn't have on the PDP-8 I used, so I won't go into those. The PDP-8 was a really amazing machine to learn from, since it had lights on the front panel which showed the state of all the internal flags and registers, as well as the instruction-execution state of the processor. Because it was so simple, it was also easy to learn to use. (Incidentally, the internal registers visible on the front panel included the accumulator, the execution state (fetch, defer, or execute), the instruction register (opcode), the memory data direction, the link, the interrupt enable flag, the memory data register, the memory address register, the actual bus contents, the interrupt request line, and a few other registers and flags having to do with bus operation.) Well, I hope the above will also bring back fond memories for other people who once knew this machine, and will help those who didn't to know a little more about this very historic machine. -------- "PDP" is a trademark of the Digital Equipment Corporation. (Incidentally, according to the PDP-8 manual, so is the phrase "Computer Lab"!) -- UUCP: Ofc: jer@peora.UUCP Home: jer@jerpc.CCUR.UUCP CCUR DNS: peora, pesnta US Mail: MS 795; CONCURRENT Computer Corp. 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