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From: berger@imag.UUCP (Gilles BERGER SABBATEL)
Newsgroups: net.arch
Subject: Re: RISC cache vs CISC u-code
Message-ID: <570@imag.UUCP>
Date: Thu, 6-Mar-86 18:42:53 EST
Article-I.D.: imag.570
Posted: Thu Mar  6 18:42:53 1986
Date-Received: Sun, 9-Mar-86 00:55:01 EST
References: <136@pyramid.UUCP>
Reply-To: berger@imag.UUCP (Gilles BERGER SABBATEL)
Organization: IMAG, Un. of Grenoble, France
Lines: 19

In article <136@pyramid.UUCP> dan@.UUCP (Dan Sobottka) writes:
>
>...  The space that is freed up on a RISC chip by having
>little if any u-code ROM can be used for more cache.  ...
>... So, having the cache effectively reduces Bus traffic not only to a CISC
>level (because of above explanation) but also probably LESS traffic because
>the cache can be used for ALL instructions (and data).
>Or am I missing something?
>
OK, but what when the system is multiprogrammed? Frequent swaps between
processes aren't likely to break the cache efficiency?   This could be
the cause of important degradation of RISC performance in multiuser
environment (Cf previous discussions about the Ridge).

... Or am I missing something?....

-- 
Gilles BERGER SABBATEL - IMAG-TIM3/INPG, GRENOBLE - FRANCE
berger@archi@imag.UUCP